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PowerQUICC II Register Programming
Table 6-7. Memory Controller Initialization For 100MHz—E 2 PROM as Boot Device
Reg.
BR4
Device Type
SM73228XG1JHBG0 by
Bus
PPC
Init Value
[hex]
C3801801
Description
Base at C3800000, 32 bit port size, no parity,
Smart Modular Tech.
GPCM
SM73248XG2JHBG0 by
Smart Modular Tech.
ASM73288XG4JHBG0
by Smart Modular Tech.
C3001801
C2001801
Base at C3000000, 32 bit port size, no parity,
GPCM
Base at C2000000, 32 bit port size, no parity,
GPCM
OR4
SM73228XG1JHBG0 by
Smart Modular Tech.
SM73248XG2JHBG0 by
Smart Modular Tech.
SM73288XG4JHBG0 by
Smart Modular Tech.
FF800876
FF000876
FE000876
8MByte block size, CS early negate, 11 w.s.,
Timing relax
16MByte block size, CS early negate, 11 w.s.,
Timing relax
32MByte block size, CS early negate, 11 w.s.,
Timing relax
BR5
PM5384 - ATM UNI
PPC
04600801
Base at 04600000, 8 bit port size, no parity, GPCM
on PPC bus.
OR5
FFFF8E56
32K Byte block size, delayed CS assertion, early
CS and WE negation for write cycle, relaxed
timing, 7 w.s. for read, 8 for write, extended hold
time after read.
BR3
PCI Interrupt Controller
PPC
04731801
Base at 04730000, 32 bit port size, no parity,
GPCM on PPC bus.
OR3
FFFF8010
32 KByte block size, all types access, 1 w.s.
Table 6-8. Memory Controller Initialization For 100MHz
Reg.
PSDMR
Device Type
MT48LC8M16A2
Bus
PPC
Init Value
[hex]
C34F36A3
Description
Page Based Interleaving, Refresh enabled, normal
(64 MByte)
Single
PowerQ
UICC II
Bus
Mode
operation mode, address muxing mode 3, A14-A16 on
BNKSEL, A7 on PSDA10, 8 clocks refresh recovery, 3
clocks precharge to activate delay, 3 clocks activate to
read/write delay, 4 beat burst length, 2 clock last data
out to precharge, 2 clock write recovery time, no extra
cycle on address phase, normal timing for control lines,
3 clocks CAS latency.
PSRT
PPC Bus
SDRAM
PPC
13
Divide MPTPR output by 20 (PSRT +1) Generates
Supported
refresh every 8.2 μ sec., while 15.6 μ sec. required. This
will work also for 66MHz bus (12.4 μ sec).
MPTPR
All SDRAMs on board
2800
Divide Bus clock by 41 (MPTPR+1) (decimal)
Chapter 6. Memory Map
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